The present invention relates to a flash memory device having a multi-level cell. More particularly, the present invention relates to a method for performing a read operation at a set voltage level irrespective of a LSB or MSB program operation of a certain cell.
Generally, flash memory is categorized into a NAND or NOR flash memory. Here, the NOR flash memory has excellent random access time characteristics because memory cells are independently connected to a bit line and a word line. Whereas, in the NAND flash memory, only one contact is required for one cell string because memory cells are serially connected and so the NAND flash memory has excellent characteristics in view of the degree of integration. Accordingly, the NAND flash memory is generally employed in highly integrated flash memory.
Recently, a multi-bit cell for storing a plurality of data in one memory cell has been actively studied for the purpose of increasing the degree of integration of the flash memory.
This memory cell is referred to as a multi-level cell (MLC). The memory cell for storing one bit is referred to as a single level cell (SLC).
Generally, the MLC may be programmed by multi-levels.
FIG. 1 is a view illustrating a threshold voltage distribution in accordance with a program of a MLC flash memory.
FIG. 1 shows the voltage distribution of the MLC for storing at least two bits programmed by the variable level method.
As shown in FIG. 1, an erase cell 110 and a program cell 120 have voltage distributions based on a voltage V1 when the least significant bit (LSB) is programmed. An extra flag cell F is included in each word line of the flash memory so as to indicate if only the LSB has been programmed (e.g., a first state 170) or if both the LSB and MSB have been programmed (e.g., a second state 180).
When the program of the most significant bit (MSB) is finished, the erase cell 110 is converted into the erase cell 130 and 140 and the program cell 120 is converted into program cells 150 to 160. Additionally, the flag cell F is programmed based on a voltage V5 (i.e., the second state 180) and so the flag cell F is used to indicate that both the most significant bit and the least significant bit have been programmed.
FIG. 2A illustrates a representation of a memory block in a MLC flash memory.
Referring to FIG. 2A, a memory cell array 200 in the MLC flash memory includes memory cells 210 and flag cells 220. Each memory cell 212 of the memory cell array is configured to store data of 2 bits or more. In FIG. 2A, each memory cell 212 is indicated as being able to store data of 2 bits for illustrative convenience. The flag cells 220 are used to indicate a program condition of the memory cells connected to the same word line, i.e., the memory cells in the same page. Each word line is coupled to a plurality of memory cells and a flag cell.
The flag cell 220 indicates whether or not a high program operation has been conducted for the corresponding page. If the flag cell 220 is in the second state 180 (see FIG. 1), a high program operation has been performed, where both the least significant bit page and the most significant bit page have been programmed. For example, when the memory cell 212 is configured to store data of 2 bits, each of the word lines WL<0> to WL<N> may perform an operation to program the least significant bit page and another operation to program the most significant bit page. If the word line WL<0> have programmed both the least significant bit page and the most significant bit page, the flag cell F is programmed to the second state 180 to indicate that the high program operation has been performed.
However, in the case that (k−1)th word line WL<k> programs only the least significant bit page, the flag cell F<k> related to the (k−1)th word line WL<k> maintains the condition of the erase cell 170 not programmed to indicate that only least significant bit page is programmed.
FIG. 2B is a view illustrating a program order of the memory block in FIG. 2A, where the programming is done in a unit of page. The memory block is connected to the word lines WL<0> to WL<N>. Each word line is connected to a plurality of memory cells and a flag cell that together define a physical page.
The multi-level cell 212 is configured to store data of N bits. Each multi-level cell 212 may be programmed to N different states by the corresponding word line. Accordingly, each physical page provides N logical pages.
The MLC flash memory performs a program in a unit of a logical page in accordance with an order set in response to inputted data. Here, the MLC flash memory programs in the order of from a first logical page to an Nth logical page in each of the word lines WL<0> to WL<N>, or performs the program in a unit of a logical page in accordance with the order set by referring to an interference between surrounding memory cells, etc.
A common method used involves controlling the program so that adjacent pages are not continuously programmed when the program is performed in a unit of the logical page.
In addition, an address counter (not shown) counts an address in accordance with the preset page order to perform the program of the inputted data.
Further, a flag cell F is programmed in accordance with a program state of the first to Nth logical pages during the program operation. As a result, the flag cell F shows information on the program state of the word line.
For example, if the first to Nth logical pages related to the first word line WL<0> in FIG. 2B have all been programmed, the flag cell F<0> is programmed to be in the second state 180. Here, the flag cell F commonly used is a SLC.
As explained above, if the memory cell stores data of N bits, the corresponding word line has N logical pages. Accordingly, the program operation has been N number of times.
For example, if the memory cell stores data of four bits, the corresponding word line would have four logical pages. As a result, the program operation would need to be performed four times to finish programming all four logical pages associated with the word line. In such a case, the flag cell F should have two SLCs to indicate four program states.
In the read operation for the flash memory cell above, the data of the flag cell F is read first to obtain the program state information. An appropriate threshold voltage is selected using the program state information of the flag cell. The selected threshold voltage is then used to read the data stored in the memory cell.
To perform the above method, the number of the SLCs included in the flag cell F should be increased according to the number of bits the memory cell is configured to store. This may reduce the number of memory cells that could be used to store data.
Additionally, since a voltage level for reading data stored in the memory cell is determined after the program state is verified by reading the flag cell F, it would be difficult to read the data stored in the memory cell if the data in the flag cell F has an error. Moreover, a time required for the read operation may be increased as the number of the flag cell F is increased.